The escalating requirements for high density and performance associated with ultra-large scale integration require responsive changes in electrical interconnected patterns, which is considered one of the most demanding aspects of ultra-large scale integration technology. High-density demands for ultra-large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. This problem is exacerbated in manufacturing semiconductor devices having a design rule of about 0.18 microns and under.
In general, semiconductor devices comprise a substrate and elements such as transistors and/or memory cells thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. The formation of interconnection layers is partly accomplished by employing conventional photolithographic techniques to form a photoresist mask comprising a pattern and transferring the pattern to an underlying layer or composite by etching the exposed underlying regions.
In accordance with conventional practices, interconnect structures comprise electrically conductive layers such as aluminum or alloys thereof. In the process of patterning the interconnect structure, an anti-reflective coating (ARC) is typically provided between the photoresist and the conductive layer to avoid deleterious reflections from the underlying conductive layer during patterning of the photoresist. The ARC can reduce the reflectivity of, for example, an aluminum metal layer to 25-30% from a reflectivity of about 80-90%. ARCs conventionally comprise materials such as silicon nitride, silicon oxynitride and titanium nitride, and are chosen for their optical properties and compatibility with the underlying conductive layer. However, many of the desirable ARCs contain basic components, such as nitrogen, which adversely interact with the photoresist material thereon during the photolithographic process.
A conventional interconnect structure is shown in FIG. 1, wherein substrate 8 has dielectric layer 10 thereon, conductive layer 12 on dielectric layer 10, ARC 14 on conductive layer 12 and a photoresist coating 16 on ARC 14. In very large scale integrated circuit applications, dielectric 10 has several thousand openings which can be either vias or lateral metallization lines where the metallization pattern serves to interconnect structures on or in the semiconductor substrate Dielectric layer 10 can comprise inorganic layers such as silicon dioxide, silicon nitride, silicon oxynitride, etc. or organic layers such as polyimide or combinations of both. Conductive layer 12 typically comprises a metal layer such as aluminum, copper, titanium, binary alloys thereof, ternary alloys, such as Al--Pd--Cu, Al--Pd--Nb, Al--Cu--Si or other similar low resistivity metal or metal based alloys, ARC 14 typically comprises a nitride of silicon or a nitride of a metal such as titanium.
To achieve high density line wiring, photoresist coating 16 is typically a deep ultraviolet (DUV) radiation sensitive photoresist capable of achieving line width resolutions of about 0.30 microns. During the photolithographic process, radiation is passed through mask 18 defining a desired conductive pattern to imagewise expose photoresist coating 16. After exposure to radiation, the photoresist layer is developed to form a relief pattern therein. It has been observed, however, that a residue remains at the photoresist interface and ARC, near the developed photoresist sidewall, resulting in a parabolic appearance, 22a and 22b, at the base of the photoresist known as "footing".
A conventional interconnect architecture after patterning of the photoresist is shown in FIG. 2. As shown, dielectric layer 10 overlays a device or a region of the semiconductor (not shown), conductive layer 12 overlays dielectric layer 10, ARC 14 overlays conductive layer 12 and a patterned photoresist, represented by photoresist line 20 overlays on ARC 14.
Photoresist line 20 of FIG. 2 further illustrates the footing phenomena where it shown that a portion of the base of the photoresist remains after patterning. The footing problem is typical of conventional photolithographic techniques employing a photoresist coating over an ARC in the manufacture of interconnections. Footing of the photoresist during patterning results in a loss of dimensional control in the subsequently patterned underlying conductive layer limiting the ability to resolve small spaces between conductive lines and thus limiting the wiring density.
Accordingly, there exists a need for a method of manufacturing a semiconductor device wherein a photoresist overlying an ARC can be accurately patterned. There is also a need for improving line width accuracy to achieve fine line conductive patterns with minimal inter-wiring spaces.